Showing 1-10 of 10 items.

mp4 [ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)

Hot：1  Size：2.51 GB  Created：2025-02-10 19:24:58  File Count：22

Get Bonus Downloads Here.url  182 B
~Get Your Files Here !/1 -Introduction.mp4  20.18 MB
~Get Your Files Here !/10 -How to design a simple ALU.mp4  46.88 MB
~Get Your Files Here !/11 -architecture of a register bank.mp4  69.11 MB
~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4  52.15 MB

mp4 [ DevCourseWeb.com ] Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

Hot：15  Size：2.11 GB  Created：2024-06-06 00:20:35  File Count：89

Get Bonus Downloads Here.url  182 B
~Get Your Files Here !/1 - UART/1 - Simple UART TX.mp4  80.11 MB
~Get Your Files Here !/1 - UART/10 - UART 16550 FIFO P4.mp4  9.11 MB
~Get Your Files Here !/1 - UART/11 - FIFO TB.mp4  30.1 MB
~Get Your Files Here !/1 - UART/12 - Design Code.html  5.45 KB

mp4 [ DevCourseWeb.com ] Udemy - Simple Axi Bus Design Using Verilog Hdl

Hot：1  Size：595.22 MB  Created：2024-02-14 16:08:53  File Count：27

Get Bonus Downloads Here.url  182 B
~Get Your Files Here !/1 - Course Introduction/1 - Introduction.mp4  22.48 MB
~Get Your Files Here !/1 - Course Introduction/2 - AMBA introduction.mp4  6.3 MB
~Get Your Files Here !/1 - Course Introduction/3 - Comparision between AHB AXI APB.mp4  12.86 MB
~Get Your Files Here !/2 - AXI bus/10 - Read process Timing diagram.mp4  15.09 MB

mp4 [ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming

Hot：17  Size：1.33 GB  Created：2022-06-06 22:18:51  File Count：34

Get Bonus Downloads Here.url  180 B
~Get Your Files Here !/01 - Introduction/001 Preview.mp4  27.07 MB
~Get Your Files Here !/01 - Introduction/001 Preview_en.vtt  4.55 KB
~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4  6.21 MB
~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication_en.vtt  1.07 KB

mp4 [ DevCourseWeb.com ] Udemy - Verilog HDL programming with practical approach

Hot：10  Size：2.82 GB  Created：2022-05-16 13:53:20  File Count：201

Get Bonus Downloads Here.url  182 B
~Get Your Files Here !/01 - Introduction to the course/001 Preview.mp4  84.59 MB
~Get Your Files Here !/01 - Introduction to the course/001 Preview_en.vtt  14.96 KB
~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground.mp4  87.84 MB
~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground_en.vtt  13.07 KB

mp4 [ TutPig.com ] Udemy - Digital Systems and Logic Design with verilog codes

Hot：45  Size：735.32 MB  Created：2022-05-09 04:18:13  File Count：29

Get Bonus Downloads Here.url  176 B
~Get Your Files Here !/1 - Start Here/1 - Introduction of Digital Systems.mp4  11.17 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/2 - Basic Definitions.mp4  15.16 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/3 - Two Value Boolean Algebra.mp4  32.06 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/4 - Basic Theorems and properties of Boolean Algebra.mp4  60.56 MB

mp4 hardware_modeling_using_verilog

Hot：2  Size：10.58 GB  Created：2019-02-03 04:11:11  File Count：281

Hardware Modeling Using Verilog/03-gettingStartedWithVerilog.mp4  223.95 MB
Hardware Modeling Using Verilog/29-someRecommendedPractices.mp4  196.17 MB
Hardware Modeling Using Verilog/39-pipelineImplementationOfAProcessorpart3.mp4  186.23 MB
Hardware Modeling Using Verilog/28-synthesizableVerilog.mp4  183.69 MB
Hardware Modeling Using Verilog/16-blocking_Non-blockingAssignmentspart1.mp4  183.16 MB